1. Field of the Invention
The present invention relates to a packet switching apparatus, and in particular to an output-buffer packet switching apparatus in which packets inputted from a plurality of input ports are multiplexed and then, based on the address information conferred to the packets, stored in buffers corresponding to a plurality of output ports, following which the packets are outputted to the output ports.
2. Description of the Related Art
All information including voice, data, and images can be converted to packets, and super-high-speed packet switching apparatus that use an abbreviated protocol for the purpose of high-volume and super-high-speed transmission as well as for conversion are attracting considerable attention. Papers on methods of constructing this type of super-high-speed packet switching apparatus include "Investigation of Converter Architecture for Asynchronous Transfer Mode" by Suzuki et al. in the Technical Research Report SSE88-60 (1988) of the Institute of Electronics, Information, and Communication Engineers. In this paper is disclosed a packet switching apparatus in which packets inputted from a plurality of input ports are time division multiplexed and transmitted to each output port, and at each output port, the desired packet is stored in a buffer memory administered according to FIFO [First In First Out] rules.
FIG. 1 shows an example of the above-described switching apparatus. This switching apparatus has four input ports and four output ports. In this packet switching apparatus, packets inputted from input ports 610-1-610-4 are parallel expanded at serial-parallel converters 620-1-620-4. The parallel expanded packets are then time division multiplexed on time division multiplexer bus 630. Address filters 640-1-640-4 discriminate the address information carried by the packets on time division multiplexer bus 630, and if the output port address corresponds to that address filter, the packet is received and stored in corresponding buffers 650-1-650-4 that are administered according to FIFO rules. If the output port address does not correspond to that address filter, reception does not occur. The received packet is read from buffers 650-1-650-4 and outputted to output ports 660-1-660-4.
In a packet switching apparatus having the composition shown in FIG. 1, there are cases in which packets from the four input ports 610-1-610-4 arrive at buffer 650-1 corresponding to output port 660-1 in the same time slot, while only one packet is outputted per time slot. Consequently, in order to output all of the packets to the output ports, a time interval of four time slots is required, and if packets addressed to output port 660-1 arrive during this time, the number of packets stored in buffer 650-1 corresponding to output port 660-1 will not decrease. For such reasons, in packet switching apparatus having buffers on the output side, packets are generally not uniformly stored among the buffers and bias has been known to occur. For this reason, there is the problem that in cases in which packets are stored unevenly and in quantity in the buffer of each output port, the capacity of each buffer must be made great in order to achieve a sufficiently low abandonment rate.